MAX3670: Loop-Filter Configuration for the MAX3670 Low-Jitter PLL Reference Clock Generator
Jun 08, 2001
Abstract: The MAX3670 low-jitter clock generator is a monolithic phase-locked loop (PLL) that uses an external
high-Q voltage-controlled oscillator (VCO) to create a very low jitter clock signal phase-locked to a system
clock input. It is ideal for SONET OC-48 or OC-192 applications requiring a very low jitter 156 MHZ or
622MHz clock signal. When used with a low-jitter voltage-controlled SAW oscillator (VCSO) or a
voltage-controlled crystal oscillator (VCX), the total system jitter can be less than 1 psrms. This design
note provides analysis and examples that address optimal PLL configuration, including external
component values, internal divider settings, and internal phase detector gain for low-jitter applications.
アプリケーションノート1032：MAX3670: Loop-Filter Configuration for the MAX3670 Low-Jitter PLL Reference Clock Generator