キーワード: single chip transceiver, T1, SCT, transceivers, SCTs, single chip 関連製品
アプリケーションノート329
DS2151 Special Modes
May 11, 2001
Abstract: Application Note 329 provides information of all special modes in the Dallas Semiconductor DS2151 T1 single chip transceiver (SCT) and how to configure them.
Special Mode #1: 3 State Outputs
When the SYSCLK pin is held high for 193 RCLK periods, all output pins, including the parallel port are 3-stated.
Special Mode #2: Allow Access Between Framer and LIU on Transmit Side
Writing 40hex to the TEST resister will invoke this mode. When enabled, the internal TLINK node is tied to the TSER pin. This access is useful in applications where it is desired to purposely corrupt the data stream before it is to be transmitted out onto the T1 line via TTIP and TRING pins. There is an exact delay from the TSER pin to the bipolar outputs of the formatter so the user has the ability to know when the needed bits appear at RCLK and RLINK pins. This delay is 10 TCLK periods.
Mode 2: DS2151 Special mode to allow access to transmit bipolar data stream.
Special Mode #3: Tap the Transmit " Receive Bipolar Data Stream
Writing 60hex (REV B ONLY) to the TEST register will invoke this mode. When enabled, the internal TLINK node is tied to the TSER pin.
Mode 3: DS2151 Special mode to tap the transmit receive bipolar data streams.
Special Mode #4: Asynchronous, Elastic Stores Operation
Writing 07hex (REV B ONLY) to the TEST Register will invoke this mode.
Mode 4: DS2151 Special mode to allow asynchronous backplane clocks.
NOTE: When using Special Mode #4 and polling data on a multi-frame boundary, an external elastic store (DS2175) should be used instead of the transmit side elastic store of the DS2151. The internal elastic store built into the DS2153 can not release data on a multi-frame boundary. A DS2175 has the ability to sync on multi-frame pulses and therefore should be used instead.
Special Mode #5: LIU Bypass
Writing 60hex (REV A), 20hex (REV B) to the TEST register will invoke this mode. When enabled, the internal TLINK node is tied to the TSER pin.
