Note: Ultimately, it is the responsibility of the end user and assembler to abide by their own design and the assembly document requirements of their industry standards. Industry standards documents can include, but are not limited to:
Association Connecting Electronics Industries (IPC)
Joint Electronic Device Engineering Council (JEDEC)
Electronic Industries Alliance (EIA)
International Electronics Manufacturing Initiative (iNEMI)
International Electrotechnical Commission (IEC)
American National Standards Institute (ANSI)
Jisso International Council (JIC)
Japan Printed Circuit Association (JPCA)
Wiring and Harness Manufacturers Association (WHMA)
Introduction
The wafer-level package (WLP) is a type of chip-scale package (CSP), which enables the IC to be attached face down to the printed circuit board (PCB) using conventional SMT assembly methods. The chip's pads connect directly to the PCB pads through individual solder balls (Figure 1). WLP technology differs from other ball grid array, leaded, and laminate-based CSPs because no bond wires or interposer connections are required. In general, underfill material is not required for WLP. However, in certain applications such as mobile devices, underfill can enhance WLP mechanical robustness. The main advantages of the WLP are a small package size, a minimized IC-to-PCB inductance, and a shortened manufacturing cycle time.
Figure 1. Photo of a 10 x 10 WLP with circuit side view
WLP Construction
Maxim's WLP chips are manufactured by building up the package interconnect structure directly on the silicon circuit substrate. A dielectric repassivation polymer film is applied over the active wafer surface. This film provides both mechanical stress relief for the ball attachment, and electrical isolation on the die surface. Vias are imaged within the polymer film, providing electrical contact to the IC bond pad.
WLP ball arrays are configured based on a regular grid with an uniform grid pitch. The solder bump material is identified by the A1 indicator in the top mark (see Figure 2 for the location of A1 in top mark). The A1 indicator for eutectic SnPb solder is a laser overlay of dual concentric circles, . For Pb-free solders, the lasered A1 indicator is a plus sign, .
Backside wafer lamination (protective polymer film) is used for all Pb-free WLP products. This polymer material is included for both mechanical and UV light protection of the backside silicon surface.
WLP Area Array Designs and Dimensions
Maxim's WLP packages are currently designed in both 0.5mm and 0.4mm pitch. Detailed WLP outline drawings are available on Maxim's Package Outlines page.
Figure 2. Package outline drawing of a 10 x 10 array WLP.
WLP Carrier Tape
Maxim ships all WLPs in the component carrier tape-and-reel (T&R) format only. WLP tape-and-reel requirements are based on the EIA-481 standard. Detailed tape-and-reel construction information is available on Maxim's SMD Tape & Reel Data page.
PCB Assembly Process Design and Implementation
Reference:
IPC-7094 Design and Assembly Process Implementation for Flip-Chip and Die Size Components
PCB Design Criteria
References:
IPC-A-600 Acceptability of Printed Boards
IPC-6011 Generic Performance Specification for Printed Boards
IPC-6012 Qualification and Performance Specification for Rigid Printed Boards
IPC-6013 Qualification and Performance Specification for Flexible Printed Boards
IPC-6016 Qualification and Performance Specification for High-Density Interconnect (HDI)
Layers or Boards
IPC-D-279 Design Guidelines for Reliable Surface-Mount Technology Printed Board Assemblies
IPC-2221 Generic Standard on Printed Board Design
IPC-2222 Sectional Design Standard for Rigid Organic Printed Boards
IPC-2223 Sectional Design Standard for Flexible Printed Boards
IPC-2226 Design Standard for High-Density Array or Peripheral Leaded Component Mounting Structures
The design layout for the WLP component should be at the most neutral location of mechanical stress and strain; it should be shrouded by much taller adjacent components, wherever possible.
For all two-sided PCB assembly designs, align a much larger compliant package on the opposite side at the WLP centroid location.
Land Pattern Design
Reference:
IPC-7351 Generic Requirements for Surface-Mount Design and Land Pattern Standard
Two types of land patterns are used for surface-mount packages (Figure 3):
Solder Mask Defined (SMD)
SMD pads are open metal surfaces with solder mask openings.
The solder mask opening is smaller than the metal pad.
Solder mask material used to define the opening is commonly LPI (liquid photoimageable) and must have suitable material properties to meet all SMT processing requirements.
NonSolder Mask Defined (NSMD).
NSMD pads are metal defined pads that have a solder mask clearance around the pad.
The solder mask opening is larger than the metal pad.
The solder mask material used to define the opening is commonly LPI (liquid photoimageable) and must have suitable material properties to meet all SMT processing requirements.
Figure 3. SMD vs. NSMD PCB land pad design for WLP.
To choose between NSMD and SMD pads, all power, ground, and signal-routing requirements must be considered.
For a given WLP pitch, the size of a NSMD pad is smaller than that of an SMD pad. Therefore, the NSMD board design allows better routability of Cu lines between pads
Also, micro-via design (i.e., "via in pad") can improve the routability of Cu lines between pads.
Use only one type of a pad layout (NSMD or SMD) and one type of pad surface finish (see below) for a given board design.
Solder mask is recommended between all pads.
The trace width connected to pads should be < 60% pad diameter.
Table 1. PCB Pad Size (in Microns) for Maxim WLP
WLP Ball Pitch
Nominal Ball Size Diameter
Nominal Pad Size Diameter Used in Maxim Package Qualification
Immersion tin plating and Hot-Air Solder Level (HASL) tin plating: not recommended.
Pb-Free Assembly PCB Material
Standard FR-4 is compatible with Maxim WLP. However, using higher glass transition (Tg) FR-4 with smaller thermal expansion coefficient (CTE) improves package reliability.
Solder Paste Print Stencil Aperture Design
Reference:
IPC-7525 Guidelines for Stencil Design
Aperture Shape
Square is preferred to round for improved solder paste release from the stencil.
The stencil aperture shape should be trapezoidal with the bottom opening (at PCB side) larger than the opening at the top of the stencil.
Solder Stencil Fabrication
Stencils can be fabricated using either of the following processes:
Laser cut of stainless steel foil with subsequent electropolishing
Electroforming of nickel-based metal foil
SMT Process Flow
INCOMING WLP TAPE -AND -REEL INSPECTION
SOLDER PASTE PRINTING ON BOARD
CHIP PLACEMENT ON BOARD
SOLDER REFLOW
FLUX CLEANING (OPTIONAL)
SOLDER JOINT INSPECTION
PACK AND SHIP
Automated Component Placement
Standard pick-and-place equipment can be used for placing Maxim WLP; fine-pitch IC-packaging placement equipment is preferred for better accuracy.
Minimum force should be used for pick and place to avoid physical damage.
To have better reflow yield, it is recommended that bumps be dipped into solder paste on the PCB to greater than 20% of paste block height.
Solder Paste Reflow
All Maxim WLPs are compatible with industry-standard solder reflow processes. For a reflow profile, reference the Pb-free solder reflow requirement in J-STD-020, Rev D.1, and any other recommendation from the paste supplier.
Nitrogen inert-atmosphere reflow soldering is optional. However, the use of nitrogen inert-atmosphere reflow has demonstrated a better centering of the Pb-free WLP on the PCB pads than in the case of reflow in air.
Rework of WLP
Rework should only be performed using a controlled and qualified process which prevents mechanical and ESD damage of the silicon circuit and package.
Focused infrared (IR) technology is recommended for ball array package rework over traditional hot gas BGA rework systems. Focused IR allows for pin-point accuracy reflow removal and replacement of even the smallest WLP parts in a high-density circuit assembly without adjacent components heating.
Thermal Performance of WLP
3-D thermal modeling has been performed to determine the junction-to-air thermal resistance, ΘJA, and junction-to-board thermal resistance, ΘJB, of Maxim WLP. See Figures 4 and 5 for standard four-layer 2s2p boards (JESD51-9). Additional data for the 1s0p boards can be found on Maxim's internal WLP engineering site. Please ask your sales representative for access to AN1891_1.
Figure 4. ΘJA vs. ball count for a 4-layer board (2s2p).
Figure 5. ΘJB vs. ball count in a 4-layer board (2s2p).
Maxim WLP Reliability
Reliability tests detailed in Table 2 are performed to qualify Maxim WLP. Data for a 6 × 6 array WLP is given in Table 3. Data for other arrays can be found on Maxim's internal WLP engineering site. Please ask your sales representative for AN1891_1.
Table 2. Reliability Qualification Requirements
Test
Specification
Test Duration
Sampling Plan
Number of Lots
MSL 1 Solder Reflow (260°C peak)
J-STD 20C
3x
0/150
3
High-Temperature Storage
JESD22 A103
1000 hours
0/77
3
Temperature Cycle
JESD22 A104, Condition G (-40°C to + 125°C)
1000 cycles (array size < = 6 x 6)
77
3
500 cycles (array size > 6 x 6)
77 (note)
3
Operating Life Test(Tj = 135°C)
JESD22 A108
1000 hours
0/77
3
Drop Test
JESD22 B111
150 cycles
60 (note)
1
Note: Less than 5% failure rate and more than 90% confidence level at the number of cycles specified for the reliability stress.
Table 3. 0.5mm Pitch 6 x 6 Array Pb-Free WLP Reliability Test Results
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. For Pb-free solders, the lasered A1 indicator is a plus sign, 
.
Backside wafer lamination (protective polymer film) is used for all Pb-free WLP products. This polymer material is included for both mechanical and UV light protection of the backside silicon surface.
