Abstract: The DS1875 burst-mode PON controller with integrated monitoring allows programming to configure the alarms, warnings, lookup tables, and other functions. The programming necessitates a large register memory map. This application note provides a simplified view of the register map, which is convenient when programming the device.
Memory Map of the DS1875
The DS1875 burst-mode PON controller features ten separate memory tables that are internally organized into 8-byte rows.
The Lower Memory is addressed from 00h to 7Fh. It contains alarm and warning thresholds, flags, masks, several control registers, password entry area (PWE), and the Table Select byte.
Table 00h contains conversion results for MON5 through MON8.
Table 01h primarily contains user EEPROM (with PW1-level access), as well as some alarm and warning status bytes.
Table 02h is a multifunction space that contains configuration registers, scaling and offset values, passwords, interrupt registers, and other miscellaneous control bytes.
Table 03h is strictly user EEPROM that is protected by a PW2-level password.
Table 04h contains a temperature-indexed LUT for controlling the modulation voltage. The modulation LUT can be programmed in 2°C increments over the -40°C to +102°C range. Access to this register is protected by a PW2-level password.
Table 05h contains a temperature-indexed LUT. It allows the APC set point to change as a function of temperature to compensate for TE (tracking error). The APC LUT has 36 entries that determine the APC setting in 4°C windows between -40°C to +100°C. Access to this register is protected by a PW2-level password.
Table 06h contains a MON4-indexed LUT for controlling the M4DAC voltage. The MON4 LUT has 32 entries that are configurable to act as one 32-entry LUT of two 16-byte LUTs. When configured as one 32-byte LUT, each entry corresponds to an increment of 1/32 of the full scale. When configured as two 16-byte LUTs, the first 16 bytes and the last 16 bytes each correspond to 1/16 of full scale. Either of the two sections is selected with a separate configuration bit. Access to this register is protected by a PW2-level password.
Table 07h contains a temperature-indexed LUT for controlling the PWM reference voltage (integration of FB input). The PWM LUT has 36 entries that determine the APC setting in 4°C windows between -40°C to +100°C. Access to this register is protected by a PW2-level password.
Table 08h contains a temperature-indexed LUT for controlling the BIAS current. The BIAS LUT can be programmed in 2°C increments over the -40°C to +102°C range. Access to this register is protected by a PW2-level password.
Auxiliary memory (Device A0h) contains 256 bytes of EE memory accessible from address 00h–FFh. It is selected with the device address of A0h.
The following tables provide an easy reference to the Lower Memory and Tables 00h, 01h, and 02h. For a description of the functionality for each bit, please refer to the corresponding register in the data sheet. Tables 03h through 08h are LUTs that do not require a separate reference and, therefore, not included here. Please refer to the data sheet for detailed information about these tables.
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