| SFR |
Bit(s) |
Differences |
| P0 |
– |
DS8xC520/DS89C430/DS89C450 only; controls Port 0 pins. |
| DPS |
4 (AID) |
DS89C430/DS89C450 only; controls the autoincrement/decrement function for the active data pointer. |
| 5 (TSL) |
DS89C430/DS89C450 only; enables automatic toggling between data pointers after certain opcodes. |
| 6 (ID0) |
DS89C430/DS89C450 only; controls the effect of INC DPTR (increment or decrement) on DPTR. |
| 7 (ID1) |
DS89C430/DS89C450 only; controls the effect of INC DPTR (increment or decrement) on DPTR1. |
| PCON |
4 (OFDE) |
DS89C430/DS89C450 only; crystal oscillator fail detection enable. |
| 5 (OFDF) |
DS89C430/DS89C450 only; crystal oscillator fail detection flag. |
| CKCON |
7 (WD1)
6 (WD0) |
On all devices except the DS80C310; these bits control the watchdog timer period. |
| EXIF |
0 (BGS) |
On all devices except the DS80C310; this bit enables/disables the bandgap reference during stop mode. |
| 1 (RGSL) |
On all devices except the DS80C310; this bit controls execution from the ring oscillator during the crystal warmup period. |
| 2 (RGMD) |
On all devices except the DS80C310; this flag indicates the current clock source (ring or crystal). |
| 3 |
DS8xC520 (XT/nRG); selects the ring oscillator or crystal as the desired clock source.
DS89C430/DS89C450 (CKRY); indicates that the crystal oscillator or crystal multiplier has completed its warmup period. |
| CKMOD |
3 (T0MH) |
DS89C430/DS89C450 only; allows Timer 0 to run directly from the system clock (clock/1). |
| 4 (T1MH) |
DS89C430/DS89C450 only; allows Timer 1 to run directly from the system clock (clock/1). |
| 5 (T2MH) |
DS89C430/DS89C450 only; allows Timer 2 to run directly from the system clock (clock/1). |
| ACON |
5 (PAGES0)
6 (PAGES1) |
DS89C430/DS89C450 only; selects the page-mode configuration for external bus operations. |
| 7 (PAGEE) |
DS89C430/DS89C450 only; enables page mode (as opposed to the standard 8051 expanded bus mode) for external bus operations. |
| IE |
6 (ES1) |
On all devices except the DS80C310; this bit enables/disables the serial port 1 interrupt. |
| SADDR1 |
– |
On all devices except the DS80C310; this register controls the slave address for serial port 1. |
| IP1 |
– |
DS89C430/DS89C450 only; this register combines with the settings in IP0/IP to provide four priority-level settings for each interrupt (as opposed to two settings with IP only). |
| SADEN1 |
– |
On all devices except the DS80C310; this register sets the slave address mask for serial port 1. |
| SCON1 |
– |
On all devices except the DS80C310; this register controls mode settings for serial port 1. |
| SBUF1 |
– |
On all devices except the DS80C310; this register provides the input/output buffer for serial port 1. |
| ROMSIZE |
2:0 (RMS2:0) |
DS8xC520/DS89C430/DS89C450 only; selects the range of on-chip EPROM/flash that maps into program space. |
| 3 (PRAME) |
DS89C430/DS89C450 only; enables/disables mapping of the 1kB internal RAM into program space. |
| PMR |
1:0 (DME1:0) |
DS8xC520/DS89C430/DS89C450 only; controls mapping of internal data memory into data space. |
| 2 |
DS8xC520 (ALEOFF); when set to 1, disables ALE during on-board memory access.
DS89C430/DS89C450 (ALEON); when set to 0, disables ALE during on-board memory access. |
| 3 |
DS8xC520 (XTOFF); when set to 1, disables the crystal oscillator (must run from ring).
DS89C430/DS89C450 (4X/n2X); sets the mode for the crystal multiplier. |
| 4 (CTM) |
DS89C430/DS89C450 only; when set to 1, enables the crystal multiplier. |
| 5 (SWB) |
DS8xC520/DS89C430/DS89C450 only; when set to 1, enables automatic switchback mode. |
| 7:6 (CD1:0) |
DS8xC520/DS89C430/DS89C450 only; controls the clock division or multiplier mode. Note that the available settings are different on the DS8xC520/DS89C430/DS89C450. |
| STATUS |
0 (SPRA0) |
DS8xC520/DS89C430/DS89C450 only; indicates that a character is currently being received on serial port 0. |
| 1 (SPTA0) |
DS8xC520/DS9C430/DS89C450 only; indicates that a character is currently being transmitted on serial port 0. |
| 2 (SPRA1) |
DS8xC520/DS89C430/DS89C450 only; indicates that a character is currently being received on serial port 1. |
| 3 (SPTA0) |
DS8xC520/DS89C430/DS89C450 only; indicates that a character is currently being transmitted on serial port 1. |
| 4 (XTUP) |
DS8xC520 only; indicates whether the crystal oscillator has completed its warmup cycle. |
| 5 (LIP) |
DS80C320/DS80C323/DS8xC520 only; indicates that a low-priority interrupt is currently being serviced. |
| 6 (HIP) |
DS80C320/DS80C323/DS8xC520 only; indicates that a high-priority interrupt is currently being serviced. |
| 7 (PIP) |
DS80C320/DS80C323/DS8xC520 only; indicates that a power-fail priority interrupt is currently being serviced. |
| 7:5 (PIS2:0) |
DS89C430/DS89C450 only; indicates that the priority level of the interrupt is being serviced. |
| TA |
– |
On all except the DS80C310; controls the Timed Access register protection mechanism. |
| WDCON |
0 (RWT) |
On all devices except the DS80C310; resets the watchdog timer. |
| 1 (EWT) |
On all devices except the DS80C310; enables/disables the watchdog timer. |
| 2 (WTRF) |
On all devices except the DS80C310; indicates that a watchdog timer reset has occurred. |
| 3 (WDIF) |
On all devices except the DS80C310; indicates that a watchdog timer interrupt has occurred. |
| 4 (PFI) |
On all devices except the DS80C310; indicates that a power-fail interrupt has occurred. |
| 5 (EPFI) |
On all devices except the DS80C310; enables/disables the power-fail interrupt. |
| 6 (POR) |
On all devices; indicates that a power-on reset has occurred. |
| 7 (SMOD_1) |
On all devices except the DS80C310; enables/disables baud-rate doubling mode for serial port 1. |
| EIE |
4 (EWDI) |
On all devices except the DS80C310; enables/disables interrupts from the watchdog timer. |
| EIP |
3:0 (PX5:2) |
On all devices except the DS89C430/DS89C450; sets high/low priority for external interrupts 2, 3, 4, and 5. |
| 4 (PWDI) |
DS80C320/DS80C323/DS8xC520 only; sets high/low priority for the watchdog timer interrupt. |
| EIP1, EIP0 |
– |
DS89C430/DS89C450 only; these registers set priority levels 0–3 for the watchdog timer interrupt and external interrupts 2, 3, 4, and 5. |
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