5タップ、高速シリコン遅延ライン

型番	ステータス
DS1004	この製品は製造を中止しています。推奨置換品についてはオーダー情報をご覧ください。

The DS1004 5-Tap High-Speed Silicon Delay Line reproduces an input logic state at the output after a minimum input-to-tap delay of 5ns at Tap 1, with Taps 2 to 5 precisely delayed by 2, 3, 4, or 5ns. Nominal delay tolerances are characterized at standard conditions of +25°C and +5V, with added tolerances over nonstandard temperature and voltage. Leading and trailing edges are reproduced with equal precision. Each tap output is capable of driving up to ten 74LS loads.

By enabling precise timing adjustments, Dallas Silicon Delay Lines improve system performance. They provide an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. Each delay line die is laser-optimized and molded into a space-saving SOIC package.

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