DS21352, DS21552

3.3V DS21352および5V DS21552 T1シングルチップトランシーバ

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ステータス 製品のステータスコードについての説明

入手可能:生産中

製品概要

The DS21352/552 T1 single chip transceiver contains all of the necessary functions for connection to T1 lines whether they are DS1 long haul or DSX-1 short haul. The clock recovery circuitry automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX-1 line build outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of internal registers which the user can access and control the operation of the unit. Quick access via the parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90), AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
 

データシート

英語 このデータシートをPDF形式でダウンロードするダウンロードする Rev 1 (PDF, 1.1MB)
  Eメール

正誤表DS21552 21552A4.pdf
正誤表DS21352 21352_Q352B2.pdf
正誤表DS21352 21352_Q352A4.pdf
正誤表DS21552 21552_Q552B1.pdf
評価キットが入手可能です:DS21352DK

主な特長

  • Complete DS1/ISDN-PRI/J1 transceiver functionality
  • Long and Short haul LIU
  • Crystal-less jitter attenuator
  • Generates DSX-1 and CSU line build-outs
  • HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation
  • Dual two-frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz
  • 8.192MHz clock output locked to RCLK
  • Interleaving PCM Bus Operation
  • Per-channel loopback and idle code insertion
  • 8-bit parallel control port muxed or nonmuxed buses (Intel or Motorola)
  • Programmable output clocks for Fractional T1
  • Fully independent transmit and receive functionality
  • Generates/detects in-band loop codes from 1 to 8 bits in length including CSU loop codes
  • IEEE 1149.1 JTAG-Boundary Scan
  • Pin compatible with DS2152/54/354/554 SCTs
  • 100-pin LQFP package (14 mm x 14 mm) 3.3V (DS21352) or 5V (DS21552) supply; low power CMOS
   
   

主な仕様:

T/E Carrier & Packetized Products
Part Number Transmission Standard Functions Channels VSUPPLY
(V)
Package/Pins Smallest Available Pckg.
(mm2)
Budgetary Price
max w/pins See Notes
DS21352  T1/J1 Framer + LIU 1 3.3
CSBGA/100
LQFP/100
100 $16.48 @1k
DS21552  5
LQFP/100
262.4 $16.48 @1k
全T/E Carrier & Packetized Products (100)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor.


DS21352、DS21552:ピン配列
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その他の情報

評価キット

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情報インデックス

Rev 1; 2000-12-07
このページの最終更新日: 2009-10-28




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