マキシム > 製品 > T/Eキャリアおよびパケット通信 > DS21Q352, DS21Q354, DS21Q552, ...

DS21Q352, DS21Q354, DS21Q552, DS21Q554

クワッドT1/E1トランシーバ(3.3V/5.0V)

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ステータス 製品のステータスコードについての説明

入手可能:生産中

製品概要

The quad T1 and E1 transceiver MCMs offer a high density packaging arrangement for the DS21352/DS21552 T1 single-chip transceivers and the DS21354/DS21554 E1 single-chip transceivers. Four silicon die of one of these devices is packaged in a multi-chip module (MCM) with the electrical connections as shown in Figure 1 in the data sheet. All of the functions available on the DS21352/DS21552 and DS21354/DS21554 are also available in the MCM packaged version however in order to minimize package size, some signals have been deleted. These differences are detailed in table 1 in the data sheet.

This data sheet describes the electrical connections and the mechanical dimensions only. Please see the DS21352/DS21552 and DS21354/DS21554 data sheets for full details on all of the features and the operating characteristics of the device.
 

データシート

英語 このデータシートをPDF形式でダウンロードするダウンロードする Rev 1 (PDF, 176kB)
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正誤表DS21Q552 21552A4.pdf
正誤表DS21Q354 21354_Q354A4.pdf
正誤表DS21Q352 21352_Q352A4.pdf
正誤表DS21Q554 21554_Q554A4.pdf
正誤表DS21Q354 21354_Q354C1.pdf
正誤表DS21Q354 21354_Q354B2.pdf
正誤表DS21Q352 21352_Q352B2.pdf
正誤表DS21Q554 21554_Q554C1.pdf
正誤表DS21Q552 21552_Q552B1.pdf

主な特長

  • Four completely independent T1 or E1 transceivers in one small 27mm x 27mm package
  • Each transceiver contains a short and long haul line interface plus a full featured framer with alarm detection/generation, elastic-stores, hardware based signaling support, per DS0 channel control and HDLC controller
  • Each multi-chip module (MCM) contains four die of
    • DS21352 (DS21Q352)
    • DS21552 (DS21Q552)
    • DS21354 (DS21Q354)
    • DS21554 (DS21Q554)
  • See the specific DS21352/DS21552 and DS21354/DS21554 data sheets for details on their feature set and operation
  • All four T1 or E1 transceivers can be concatenated into a single 8.192MHz backplane data stream
  • IEEE 1149.1 JTAG-Boundary Scan architecture
  • DS21Q352/DS21Q552 and DS21Q354/DS21Q554 are pin compatible to allow the same footprint to support T1 and E1 applications
  • 256-pin MCM BGA package (27mm X 27mm)
  • Low power 5V CMOS or low power 3.3V CMOS with 5V tolerant input and outputs
   
   

主な仕様:

T/E Carrier & Packetized Products
Part Number Transmission Standard Functions Channels VSUPPLY
(V)
Package/Pins Smallest Available Pckg.
(mm2)
Budgetary Price
max w/pins See Notes
DS21Q352  T1/J1 Framer + LIU 4 3.3
PBGA/256
729 $61.80 @1k
DS21Q354  E1 3.3
PBGA/256
$77.14 @1k
DS21Q552  T1/J1 5
PBGA/256
$77.14 @1k
DS21Q554  E1 5
PBGA/256
$77.14 @1k
全T/E Carrier & Packetized Products (99)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor.


DS21Q352、DS21Q354、DS21Q552、DS21Q554:回路図
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情報インデックス

Rev 1; 1998-12-29
このページの最終更新日: 2009-12-17




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