QuicKic Layout With Verification
QuicKic is a netlist-driven IC layout editor that checks process design rules, connectivity, and interconnect parasitics as the layout is being performed. IC layout is fast and error free because QuicKic leads the designer through the layout process by highlighting nodes to be connected and preventing improper connections. Highlights of QuicKic include:
- Netlist-driven layout for elements and interconnect
- Error-locating interfaces
- Real-time and batch process design-rule checking (DRC)
- Multilevel undo and redo
- Real-time and batch connectivity checking
- Interconnect parasitic capacitance and resistance extraction
- Automatic custom device generation for capacitors, resistors, and diodes
Process design rules are automatically checked during layout, and violations are immediately highlighted. QuicKic automatically generates custom devices according to the parameters in the netlist. Interfaces are provided to generate parameterized capacitors, diodes and resistors.
QuicKic allows you to extract parasitic interconnect capacitance and resistance directly from the layout. You can interactively inspect interconnect parasitics and write them to a file for circuit resimulation. And, capacitance interface allows you to extract both node-to-substrate and node-to-node overlap capacitance. The resistance interface allows point-to-point interconnect resistance to be probed on any node.
HIGHLIGHTED CONNECTIVITY ERRORS
HIGHLIGHTED PROCESS DESIGN RULE VIOLATIONS
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