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マキシム >
製品 >
T/Eキャリアおよびパケット通信
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ATM Packet PHYs
Industry's First Multiport T3/E3 ATM/Packet PHYs with Built-in Line Interface Units
The DS3184 (quad) is 75% smaller, 32% lower power, and 33% lower cost than existing DS3/E3 solutions!
The DS318x family provides fully integrated DS3/E3 PHYs, including the LIUs. The DS318x family consists of the DS3184 (quad), DS3183 (triple), DS3182 (dual), and DS3181 (single). The Universal PHYs map ATM cells and/or HDLC packets into DS3 or E3 data streams. The DS316x family is a line of multiport DS3/E3 ATM/Packet PHYs without LIUs. All eight DS318x and DS316x devices are pin- and software-compatible for easy port density migration on a single PCB design.
Further Improvements Over the Competition
- Subrate (or fractional) DS3 supported with internal circuitry and special external interfaces
- System interface options include UTOPIA 2/3 and POS-PHY 2/3 with 8-, 16-, or 32-bit bus width up to 66MHz
- Integrated clock rate adapter to generate required frequencies from single DS3/E3/STS-1 reference frequency
Other Key Features
- All ports are independently configurable for DS3, E3, or external framing protocols up to 52 Mbps
- Direct, PLCP, and clear channel cell mapping supported
- Direct and clear channel packet mapping supported
- Each port can be disabled to reduce power
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