The DS21Q41B packs four independent, enhanced (indicated by the "B") DS2141 T1 framers onto one die. The four framers share a common port for control and data communication. The DS21Q41B uses the DS1241 register structure and has two framer-select inputs for separate framer access so that software written for the DS2141 can be reused for the DS21Q41B.
Like the DS2141, the DS21Q41B has separate, programmable receive and transmit sides, dual two-frame elastic stores, and a parallel control port. Features new to the DS21Q41B include the option for nonmuxed bus operation; an ANSI 1s density monitor (both sides) and enforcer (transmit side); CSU loop code generator; elastic store reset and minimum delay mode; support for D4 to ESF conversion; separable receive/transmit elastic stores; TCLK keep-alive; and excessive 0 counting (EXZs).
The DS21Q41B meets ANSI T1.403 and T1.403-199X, ANSI T1.231-1993, AT&T TR62411 and TR54016, ITU G.704, and G.706.
Applications include Channelized T3, frame relay or ATM WAN access, monitoring and testing equipment, optical multiplexers, and SONET Add-Drop Multiplexers.
主な特長
Four independent T1 DS1/ISDN-PR1 framers
Frames to D4, ESF, and SLC-96 formats
8-bit parallel control port can connect to muxed or nonmuxed buses
Each framer has dual two-frame elastic stores that can connect to asynchronous or synchronous backplanes up to 8.192MHz
Extracts/inserts robbed-bit signals
Framer and payload loopbacks
Large BPV, LCV, EXZ, CRC6, PCV, F-bit error, and out-of-sync multiframe counters
ANSI 1s density monitor/enforcer
CSU loop code generator/detector
Programmable output clocks for Fractional T1, ISDN-PRI, Actual Size, and per-channel loopback applications
ダウンロードする