The DS87C530/DS83C530 EPROM/ROM microcontrollers with a real-time clock (RTC) are 8051-compatible microcontrollers based on the Dallas Semiconductor high-speed core. They use 4 clocks per instruction cycle instead of the 12 used by the standard 8051. They also provide a unique mix of peripherals not widely available on other processors. They include an on-chip RTC and battery backup support for an on-chip 1k x 8 SRAM. The new Power Management Mode allows software to select reduced power operation while still processing.
A combination of high-performance microcontroller core, RTC, battery-backed SRAM, and power management makes the DS87C530/DS83C530 ideal for instruments and portable applications. They also provide several peripherals found on other Dallas high-speed microcontrollers. These include two independent serial ports, two data pointers, on-chip power monitor with brownout detection and a watchdog timer.
Power Management Mode (PMM) allows software to select a slower CPU clock. While default operation uses four clocks per machine cycle, the PMM runs the processor at 64 or 1024 clocks per cycle. There is a corresponding drop in power consumption when the processor slows.
The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE signal when it is unneeded.
The DS83C530 is a factory mask ROM version of the DS87C530 designed for high-volume, costsensitive applications. It is identical in all respects to the DS87C530, except that the 16kB of EPROM is replaced by a user-supplied application program. All references to features of the DS87C530 will apply to
the DS83C530, with the exception of EPROM-specific features where noted. Please contact your local Dallas Semiconductor sales representative for ordering information.
Note: The DS87C530/DS83C530 are monolithic devices. A user must supply an external battery or super cap and a 32.768kHz timekeeping crystal to have permanently powered timekeeping or nonvolatile RAM. The DS87C530/DS83C530 provide all the support and switching circuitry needed to manage these
resources.
主な特長
80C52 Compatible
8051 Instruction-Set Compatible
Four 8-Bit I/O Ports
Three 16-Bit Timer/Counters
256 Bytes Scratchpad RAM
Large On-Chip Memory
16kB EPROM (OTP)
1kB Extra On-Chip SRAM for MOVX
ROMSIZE Features
Selects Effective On-Chip ROM Size from 0 to 16kB
Allows Access to Entire External Memory Map
Dynamically Adjustable by Software
Useful as Boot Block for External Flash
Nonvolatile Functions
On-Chip Real-Time Clock with Alarm Interrupt
Battery Backup Support of 1kB SRAM
High-Speed Architecture
4 Clocks/Machine Cycle (8051 = 12)
Runs DC to 33MHz Clock Rates
Single-Cycle Instruction in 121ns
Dual Data Pointer
Optional Variable Length MOVX to Access Fast/Slow RAM /Peripherals
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