The MAX3678 is a low-jitter frequency synthesizer with intelligent dynamic clock switching optimized for systems where redundant clock failover switching is needed. It contains a monolithic phase-locked loop (PLL) that accepts two reference clock inputs and generates nine phase-aligned outputs. The device continuously monitors the signal status for both reference clock inputs. In the event that the primary clock fails, the PLL automatically switches to the secondary clock input without generating a phase bump at the clock outputs, using a glitchless switchover mechanism. A manual switch mode is also provided for user-controlled switching. The device features ultra-low jitter generation of 0.3psRMS (integrated 12kHz to 20MHz) and excellent power-supply noise rejection.
The MAX3678 operates from a single +3.3V supply and typically consumes 400mW. The operating temperature range is from 0°C to +85°C, and is available in a 8mm x 8mm, 56-pin TQFN package.
主な特長
Two Reference Clock Inputs: LVPECL
Nine Phase-Aligned Clock Outputs: LVPECL
Automatic or Manual Dynamic Switching Between Two Reference Clock Inputs
