低電力3.3V、2.5/2.7Gbps、4:1シリアライザ、クロックシンセサイザ付
SUNNYVALE, CA-December 5, 2001-Maxim Integrated Products announces the MAX3892 3.3V, 2.5Gbps/2.7Gbps 4:1 serializer with clock synthesis and LVDS inputs. The MAX3892 is ideal for converting 4-bit-wide 622Mbps parallel data to 2.5Gbps serial data in DWDM and SDH/SONET applications. It forms a complete two-chip 2.5Gbps/2.7Gbps transceiver solution when used with the MAX3882* 1:4 deserializer with clock recovery.
Operating from a single 3.3V supply, the MAX3892 accepts 622Mbps LVDS parallel data inputs and delivers differential CML serial data and clock outputs while consuming only 455mW of power. A 4-bit x 4-bit FIFO allows for any static delay between the parallel input clock and the internally synthesized clock. Delay variation up to a unit interval is allowed over temperature. A fully integrated PLL synthesizes an internal 2.5GHz serial clock from a 622.08MHz, 155.52MHz, 77.76MHz, or 38.88MHz reference clock. A selectable dual VCO allows excellent jitter performance at both SONET and forward error correction (FEC) data rates. Excellent jitter generation performance (1.3psRMS) provides wide margin relative to the ITU/Bellcore SDH/SONET specification. A loopback data output is provided to facilitate system diagnostic testing.
The MAX3892 is available in a 44-pin QFN package over the extended temperature range (-40°C to +85°C), and is priced at $31.63 (1000-up, FOB USA). Evaluation kits are available.
*Future product— contact factory for availability.
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